Numerous integrated circuit devices, structures and techniques of fabricating same, are known to the prior art. The following prior art U.S. patents are submitted to generally represent the state of the art:
U.S. Pat. No. 3,574,008 entitled "Mushroom Epitaxial Growth In Tier-Type Shaped Holes" granted Apr. 6, 1971 to E. J. Rice,
U.S. Pat. No. 3,655,457 entitled "Method of Making or Modifying a PN-junction by Ion Implantation" granted Apr. 11, 1972, to M. C. Duffy et al,
U.S. Pat. No. 3,796,613 entitled "Method of Forming Dielectric Isolation for High Density Pedestal Semiconductor Devices" granted Mar. 12, 1974 to I. E. Magdo et al,
U.S. Pat. No. 3,975,221 entitled "Low Capacitance V Groove NOR Gate and Method of Manufacture" granted Aug. 17, 1976 to T. J. Rodgers,
U.S. Pat. No. 4,047,217 entitled "High-Gain, High-Voltage Transistor Integrated Circuits" granted Sept. 6, 1977 to T. McCaffrey et al,
U.S. Pat. No. 4,048,649 entitled "Superintegrated V-Groove Isolated Bipolar and VMOS Transistors" granted Sept. 13, 1977 to R. Bohn, and the
U.S. Pat. No. 4,080,619 entitled "Bipolar Type Semiconductor Device" granted Mar. 21, 1978 to K. Suzuki.
The present trend in semiconductor technology is toward very large scale integration of devices with very high speed and low power requirements. The parameters that are essential to such high performance bipolar transistors are low parasitic capacitances as realized by a shallow vertical junction structure and small horizontal geometry. To achieve these goals it is necessary to make the devices in the integrated circuits as small as possible.
With the advances in semiconductor processing technologies, such as in the fields of ion implantation, deep dielectric isolation, electron beam and x-ray lithographies, reactive ion etching, advanced insulator and polysilicon deposition techniques, and metal lift-off processes, fabrication of the ultrahigh performance integrated circuit devices can be achieved.
Ion implantation provides a means for precisely controlling the total amount of impurity transferred to the wafer. The impurity depth distribution is accurately controlled by implant energy. Unlike the conventional thermal diffusion process ion implantation is not a high temperature process. Thus, by using photoresist or metal masking, multiple impurity introduction operations can be achieved without resort to high temperatures. A final thermal drivein diffusion is sufficient to anneal out the radiation damage caused by implantation, and obtain desired device junction depth. Consequently, integrated circuit devices can be made shallower, with greater precision of the impurity distribution using ion implantation technology.
As the semiconductor devices become shallower, it is desirable to reduce the overall junction area so as to reduce parasitic capacitance. Further reduction of device parasitic capacitance can be achieved by shrinking of device horizontal dimensions and using dielectric isolation. Dielectric isolation is a method of fabricating integrated circuits in which the device components are isolated by other than P-N junctions. A well known dielectric isolation, namely "Recessed Oxide Isolation" (ROI) is a commonly used process in present day technology. Using Si.sub.3 N.sub.4 as the oxidation barrier, the ROI technique is done by etching grooves into the semiconductor wafer adjacent those regions in which PN junctions are to be formed. The silicon exposed by the grooves is then thermally oxidized to form recessed oxide regions providing dielectric isolation. The problem associated with the ROI is the formation of "bird's head" or "bird's beak" structure at the lateral edges of recessed oxide. The bird's head is undesirable because it can cause breaks or discontinuities in thin films covering the steps. The indefiniteness of bird's beak structure reduces the available active surface area and, therefore, imposes the need for wider tolerance of lateral dimension in the integrated circuit layout. A newly developed oxide isolation technique called "Deep Dielectric Isolation" (DDI) avoids the above mentioned problem. The DDI process utilizes reactive-ion etching (RIE) to form deep narrow trenches into the wafer surrounding those regions in which devices are to be formed. (Reference is made to U.S. Pat. No. 4,104,086, entitled "Method for Forming Isolated Regions of Silicon Utilizing Reactive Ion Etching" granted Aug. 1, 1978 to J. A. Bondur et al., and U.S. Pat. No. 4,139,442 entitled "Reactive Ion Etching Method For Producing Deep Dielectric Isolation in Silicon" granted Feb. 13, 1979 to J. A. Bondur et al., respectively assigned to the assignee of the subject application.) The trenches are overfilled with SiO.sub.2 put down by chemical vapor deposition (CVD) technique. The overfilled SiO.sub.2 also planarizes the device surface. A blanket RIE backetching to the semiconductor surface yields deep oxide isolation trenches. Unlike the bird's beak in ROI structures, sidewalls of the DDI structures are nearly vertical. The surface of DDI regions and the silicon where they are to be formed are coplanar. With the DDI, doping processes for various device regions are then self-aligned by oxide isolation. The self-aligned process eliminates precise mask alignment steps and also saves a number of mask steps in the device fabrication.
As mentioned above, DDI enables us to form devices with considerably smaller cell size than those formed by using either P-N isolation or by ROI. Further reduction of device horizontal dimensions requires the use of high resolution capabilities of lithography and etching processes. The electron beam lithography is the most promising method for delineating submicron size device patterns. For device window openings the reactive ion etch (RIE) is the most attractive alternative to the conventional wet solution etching. The RIE is a dry process having a directional etching characteristic. The etched device windows preserve the lithography defined etch mask dimensions, and the openings have vertical sidewalls. Thus, the E-beam lithography and reactive ion etching are compatible for fabricating very small device geometries.
For the very small bipolar transistor devices, as for example, micron size transistors, the base areas and, therefore, the collector-base parasitic capacitance is the most significant performance parameter. In the bipolar transistor the active base area is the region below the emitter. In the conventional transistors, fabricated in accordance with the prior art, the base contacts are formed above the inactive base area surrounding the emitter. The transistor base area that is needed to accommodate the emitter and base contacts is considerably larger than the active base area. To reduce the base area for making ultra-high performance bipolar transistors, a different approach in providing the base contact is desirable.